1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present invention relates to a fin type metal oxide semiconductor field effect transistor (MOSFET), and a method for manufacturing the fin type MOSFET.
A claim of priority is made to Korean Patent Application No. 10-2004-0006524 filed on Feb. 2, 2004, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
Modern semiconductor devices typically have high response speeds, low power consumptions, and high degrees of integration. MOSFETs commonly use a reduced channel length to attain higher response speeds. However, where the channel length is decreased in a conventional MOSFET having a planar structure, the channel driving force often decreases and an electric field caused by a drain voltage have an increased effect on the performance of the MOSFET, thereby causing a short channel effect in the conventional planar type MOSFET. Accordingly, to reduce the short channel effect and to ensure a high degree of integration, a fin type MOSFET has been developed.
The fin type MOSFET generally includes a three-dimensional channel region. In particular, the fin type MOSFET has a fin shaped active region and a gate structure enclosing the fin shaped active region. In other words, the gate electrode of the gate structure is formed on a sidewall of the fin shaped active region as well as on an upper face of the active region. As a result, the fin type MOSFET has the three-dimensional channel formed between the gate electrode and the fin shaped active region so that the short channel effect is minimized in the fin type MOSFET.
A conventional fin type MOSFET is disclosed, for example, in U.S. Pat. No. 6,413,802 issued to Hu et al. Hu discloses a MOSFET having a plurality of thin fin channels provided between source/drain regions on a semiconductor substrate. However, since this fin type MOSFET is formed on a silicon-on-insulator (SOI) substrate, it may have an increased manufacturing cost. In addition, a floating body effect may occur in the fin type MOSFET because the body of the MOSFET does not directly contact the SOI substrate. As a result, the MOSFET may be deteriorated due to heat generated therein because the heat is not easily transferred from the body of the MOSFET.
Japanese Laid Open Patent Publication No. 2002-110963 discloses a method of manufacturing a fin type MOSFET on a bulk silicon substrate. In the method of manufacturing the fin type MOSFET, a fin shaped active region having relatively large height is formed on the bulk silicon substrate. However, a gate structure is typically imprecisely formed on the fin shaped active region due to a relatively high step generated between the fin shaped active region and adjacent portions of the bulk silicon substrate. Hence, etched residues generated in the etching process for the gate structure typically remain on or near the fin shaped active region, causing an electrical failure of the fin type MOSFET. Additionally, the junction capacitance of the fin type MOSFET often increases because impurities used to form a channel region are implanted into undesired portions of the bulk silicon substrate.